The field of the invention is that of integrated circuit processing, in particular DRAM cells having vertical pass transistors.
In the fabrication of vertical-transistor DRAM cells, both in DRAMs and in DRAM arrays in ASICs and other complex systems, the formation of the capacitor removes silicon from the trench walls in the upper part of the trench, producing an overhang of the pad nitride.
That overhang interferes with filling the upper part of the trench with the gate electrode, leaving voids in the gate electrode that are disadvantageous.
Further, for a given ground rule and inter-cell spacing, the space for bitline contacts to the upper electrode of the vertical transistor is limited. The removal of silicon from the upper trench walls further reduces the width of the bitline contacts, extending outward from the trench walls into the silicon well.
Expanding the width of the cell to accommodate a wider trench and a wider bitline contact is not an option, given the overwhelming need to reduce the transverse dimensions of the cells.
As the demand for higher performance devices increases steadily, one attractive option is the use of strained silicon to improve electron mobility.